An ESD element is essential in terms of reliability though it is irrelevant to a function of an IC. The ESD element is an electrostatic discharge element configured to discharge static electricity such that the IC does not break down by the static electricity.
Accordingly it is essential that the ESD element itself does not thermally break down by static electricity and protects the internal circuit by drawing charges promptly before static electricity enters an internal circuit. In order to satisfy those conditions, suppression of local heat generation and high driving capability are required to ESD element characteristics.
NMOS transistors as illustrated in FIG. 8A to FIG. 8C are a typical ESD protection circuit. FIG. 8A is a plan view, FIG. 8B is a sectional view taken along the line A-A′, and FIG. 8C is an equivalent circuit. Gate electrodes 1 to 6 and N+ sources 11 of the NMOS transistors are connected, via wiring 17, to a Vss terminal having a lower power supply potential, and N+ drains 12 of the NMOS transistors are connected to a pad via wiring 18. The NMOS transistors are in a P-well 14. The P-well 14 has P+ regions 13 for fixing a P-well potential for the purpose of fixing the potential, and is connected to the wiring 17 having a Vss potential via a contact 16. The expression of N+ or P+ implies, in addition to a conductivity type of a semiconductor, that an impurity concentration of a region indicated with N+ or P+ is higher than that of a region indicated with N or P and is a concentration with which an ohmic contact with metal wiring can be generally formed. A “heavily doped N-type drain” has the same meaning as an “N+ drain”.
Static electricity injected into the pad causes a breakdown in the N+ drains 12 to generate positive holes. The positive holes raises the potential of the P-well 14 to induce parasitic bipolar action of the NMOS transistors to dissipate static electricity from the N+ drains 12 to the N+ sources 11. Thus, such NMOS transistors are known to have an ESD tolerance that is higher than that of a diode ESD element.
Meanwhile, there is a problem specific to this structure. As disclosed in Patent Literature 1, the P-well 14 is of a high resistance, and thus, positive holes accumulate in the P-well in the vicinity of a transistor away from the P+ regions 13 for fixing a P-well potential for the purpose of fixing the potential of the P-well 14, and parasitic bipolar action is liable to occur. There arises a problem in that current concentrates on a transistor away from the P+ region 13 for fixing a P-well potential, and an ESD tolerance cannot be obtained as intended.
As can be seen from FIG. 8B, transistors having the gate electrodes 3 and 4 are farthest from the P+ regions 13 for fixing the P-well potential, transistors having the gate electrodes 1 and 6 are closest thereto, and transistors having the gate electrodes 2 and 5 are at an intermediate distance. A LOCOS oxide film 10 for separation exists between a transistor on each side and the P+ region 13 for fixing the well potential, and a gate insulating film 15 is arranged under each gate electrode. Further, as illustrated in FIG. 8C, P-well parasitic resistances Rpw1, Rpw2, and Rpw3 exist between Vss and a P0 well 14 immediately below the transistors having the gate electrodes 1 and 6, the transistors having the gate electrodes 2 and 5, and the transistors having the gate electrodes 3 and 4, respectively. The parasitic resistances correspond to distances from the respective transistors to the P+ regions 13 for fixing a P-well potential, and thus, the following relationship holds.Rpw1<Rpw2<Rpw3
Accordingly it is the transistors having the gate electrodes 3 and 4 with the parasitic resistances Rpw3 that are most liable to cause a parasitic bipolar action. Current-voltage characteristics of the transistors are thus shown by I-V characteristics 52 in FIG. 8D and current concentration occurs. The transistors having the gate electrodes 2 and 5 and the transistors having the gate electrodes 1 and 6 show I-V characteristics 51 and 50 respectively.
A solution has been shown in an invention disclosed in Patent Literature 1. FIG. 9A to FIG. 9C are conceptual illustrations of the invention. FIG. 9A is a plan view, FIG. 9B is a sectional view taken along the line B-B′, and FIG. 9C is an equivalent circuit. Further, with reference to FIG. 9A, a pad electrode 18 is assumed to be not floating, but connected to a pad via an upper layer electrode.
When FIG. 8A to FIG. 8C and FIG. 9A to FIG. 9C are compared, in FIG. 9A to FIG. 9C, the gate electrodes 1 to 6 are not directly connected to a Vss electrode 17 to which first P+ regions 23 for fixing a P-well are connected. Through connection of the gate electrodes 1 to 6 and a second P+ region 24 for fixing a P-well via an electrode 20 connecting the second P+ region 24 for fixing a P-well and the gate electrodes, a parasitic resistance Rpw9 of the P-well 14 is added between the gate electrodes 1 to 6 and Vss. Rpw4 to Rpw9 are P-well parasitic resistances and the following relationship holds.Rpw4<Rpw5<Rpw6<Rpw7<Rpw8<Rpw9
A potential of the P-well 14 in the vicinity of the second P+ region 24 for fixing a P-well that rises the most when ESD current flows into the pad is thereby transmitted to the gate electrodes 1 to 6, and channel current flows between the N+ drains 12 and the N+ sources 11 of all the transistors. As a result, an effect of preventing current concentration is obtained.